Verilog语法中parameter与localparam的区别

注:parameter可用作在顶层模块中例化底层模块时传递参数的接口,localparam的作用域仅仅限于当前module,不能作为参数传递的接口。

`timescale 1ns/100ps

module mem (

clka,
wea,
addra,
dina,

clkb,
addrb,
doutb);

parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 5;
localparam DW = DATA_WIDTH - 1;
localparam AW = ADDR_WIDTH - 1;

input clka;
input wea;
input [AW:0] addra;
input [DW:0] dina;

input clkb;
input [AW:0] addrb;
output [DW:0] doutb;

reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)];
reg [DW:0] doutb;

always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end

always @(posedge clkb) begin
doutb <= m_ram[addrb];
end

endmodule

在顶层文件中例化mem module时可以这样做:
mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6))
i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));

也可以将底层模块的parameter参数置于module端口声明之前,例如:

`timescale 1ns/100ps
module mem
#(parameter DATA_WIDTH = 16
parameter ADDR_WIDTH = 5)
(
input clka,
input wea,
input [AW:0] addra,
input [DW:0] dina,
input clkb,
input [AW:0] addrb,
output [DW:0] doutb
);

localparam DW = DATA_WIDTH - 1;
localparam AW = ADDR_WIDTH - 1;

reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)];
reg [DW:0] doutb;

always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end

always @(posedge clkb) begin
doutb <= m_ram[addrb];
end

endmodule

原文链接: https://blog.csdn.net/yang2011079080010/article/details/51507904