Xilinx加法器IP核adder

1.加法器IP核配置

2.adder_top.v代码
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:20:30 07/19/2017
// Design Name:
// Module Name: adder_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module adder_top(
input clk,
input [7:0] x1_in,
input [7:0] x2_in,
output [7:0] y_out
);

/*always@(posedge clk)
begin
y_out = x1_in + x2_in;
end
*/

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
adder adder_instance (
.a(x1_in), // input [7 : 0] a
.b(x2_in), // input [7 : 0] b
.clk(clk), // input clk
.s(y_out) // output [7 : 0] s
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

endmodule

3.adder_top_tb.v代码
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:41:36 07/19/2017
// Design Name: adder_top
// Module Name: E:/LTE/project/S6CardXilinxFPGA/project_shgao/adder_demo/adder_top_tb.v
// Project Name: adder_demo
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: adder_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_test;

// Inputs
reg clk;

reg [7:0] x1_in;
reg [7:0] x2_in;

// Outputs

wire [7:0] y_out;

// Instantiate the Unit Under Test (UUT)
adder_top uut (
.clk(clk),
.x1_in(x1_in),
.x2_in(x2_in),
.y_out(y_out)
);

initial
begin
clk = 0;

x1_in = 8'h1;
x2_in = 8'h1;
end

always #5 clk = !clk;//clk

always@(posedge clk)
begin
if(x1_in < 8'hff)
x1_in = x1_in + 1;
else
x1_in = 0;

if(x2_in < 8'hff)
x2_in = x2_in + 1;
else
x2_in = 0;
end

endmodule

4.仿真图

注意在IP核配置时有个Latency选项,所以造成红框中的现象,在第105ns的上升沿时输出数据才发生变化。http://www.cnblogs.com/youngforever/p/3141216.html

(1)输入数据与该数据经过处理后的结果输出之间的延时,是时钟延迟;
(2)一般以时钟为单位,指的是相对于某个时钟起始位置的1个或多个时钟后数据才有效;
(3)决定信号处理的响应速度。

5.仿真时间设置

文章转载自: https://blog.csdn.net/gsh_hello_world/article/details/75463317