基于ZYNQ(Miz702)的EMIO与MIO联合操作(寄存器版)

在ZYNQ中,EMIO标号紧随MIO(0:53)之后,我定义了8个EMIO,采用标号54:61。

在PS MIO Configuration中启用GPIO MIO 勾选EMIO GPIO(Width)选项,并设置宽度为8,即设置EMIO输出到8个PL的GPIO。

具体程序如下:

penguin_sopc.h 该文件定义了关于GPIO控制器的部分寄存器的基地址

penguin_sopc.h
*
* Created on: 2017年5月4日
* Author: Penguin
*/

#ifndef PENGUIN_SOPC_H_
#define PENGUIN_SOPC_H_

#define PENGUIN_XINT_DIS_OFFSET 0x00000214
#define PENGUIN_XINT_DIS_BANK_OFFSET 0x00000040

#define PENGUIN_XINT_DIS0_ADDR (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_XINT_DIS_OFFSET+(0*PENGUIN_XINT_DIS_BANK_OFFSET))
#define PENGUIN_XINT_DIS1_ADDR (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_XINT_DIS_OFFSET+(1*PENGUIN_XINT_DIS_BANK_OFFSET))
#define PENGUIN_XINT_DIS2_ADDR (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_XINT_DIS_OFFSET+(2*PENGUIN_XINT_DIS_BANK_OFFSET))
#define PENGUIN_XINT_DIS3_ADDR (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_XINT_DIS_OFFSET+(3*PENGUIN_XINT_DIS_BANK_OFFSET))

#define PENGUIN_DIRM_0_OFFSET 0x00000204
#define PENGUIN_DIRM_0 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DIRM_0_OFFSET)

#define PENGUIN_DIRM_1_OFFSET 0x00000244
#define PENGUIN_DIRM_1 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DIRM_1_OFFSET)

#define PENGUIN_DIRM_2_OFFSET 0x00000284
#define PENGUIN_DIRM_2 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DIRM_2_OFFSET)

#define PENGUIN_DIRM_3_OFFSET 0x000002C4
#define PENGUIN_DIRM_3 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DIRM_3_OFFSET)

#define PENGUIN_OEN_0_OFFSET 0x00000208
#define PENGUIN_OEN_0 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_OEN_0_OFFSET)

#define PENGUIN_OEN_1_OFFSET 0x00000248
#define PENGUIN_OEN_1 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_OEN_1_OFFSET)

#define PENGUIN_OEN_2_OFFSET 0x00000288
#define PENGUIN_OEN_2 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_OEN_2_OFFSET)

#define PENGUIN_OEN_3_OFFSET 0x000002C8
#define PENGUIN_OEN_3 (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_OEN_3_OFFSET)

#define PENGUIN_DATA_0_LSW_OFFSET 0x00000000
#define PENGUIN_DATA_0_HSW_OFFSET 0x00000004

#define PENGUIN_DATA_1_LSW_OFFSET 0x00000008
#define PENGUIN_DATA_1_HSW_OFFSET 0x0000000C

#define PENGUIN_DATA_2_LSW_OFFSET 0x00000010
#define PENGUIN_DATA_2_HSW_OFFSET 0x00000014

#define PENGUIN_DATA_3_LSW_OFFSET 0x00000018
#define PENGUIN_DATA_3_HSW_OFFSET 0x0000001C

#define PENGUIN_DATA_0_LSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_0_LSW_OFFSET)
#define PENGUIN_DATA_0_HSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_0_HSW_OFFSET)

#define PENGUIN_DATA_1_LSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_1_LSW_OFFSET)
#define PENGUIN_DATA_1_HSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_1_HSW_OFFSET)

#define PENGUIN_DATA_2_LSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_2_LSW_OFFSET)
#define PENGUIN_DATA_2_HSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_2_HSW_OFFSET)

#define PENGUIN_DATA_3_LSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_3_LSW_OFFSET)
#define PENGUIN_DATA_3_HSW (XPAR_PS7_GPIO_0_BASEADDR+PENGUIN_DATA_3_HSW_OFFSET)

#endif /* PENGUIN_SOPC_H_ */

mian.c主程序

#include
#include "xgpiops.h"
#include "sleep.h"
#include "penguin_sopc.h"

int main()
{

    u32 Value=0;
    u8 i=0;

    //PS--MIO的初始化 主要是禁用外部中断
    Xil_Out32(PENGUIN_XINT_DIS0_ADDR,0XFFFFFFFFU);
    Xil_Out32(PENGUIN_XINT_DIS1_ADDR,0XFFFFFFFFU);
    Xil_Out32(PENGUIN_XINT_DIS2_ADDR,0XFFFFFFFFU);
    Xil_Out32(PENGUIN_XINT_DIS3_ADDR,0XFFFFFFFFU);

    Xil_Out32(PENGUIN_DIRM_0,(Xil_In32(PENGUIN_DIRM_0)|((u32)1     Xil_Out32(PENGUIN_OEN_0,(Xil_In32(PENGUIN_OEN_0)|((u32)1

    Xil_Out32(PENGUIN_DIRM_2,(Xil_In32(PENGUIN_DIRM_2)|0xff));////设置bank3 EMIO 0:7为输出
    Xil_Out32(PENGUIN_OEN_2,(Xil_In32(PENGUIN_OEN_2)|0xff));//使能bank3 EMIO 0:7输出

    while(1)
    {
        Xil_Out32(PENGUIN_DATA_0_LSW,~((u32)1         Value = ~((u32)1         Xil_Out32(PENGUIN_DATA_2_LSW,Value);//直接寄存器操作
        usleep(500000);//延时

        i++;
        if(i>7)
        {
            i=0;
            Value =0 ;
            Xil_Out32(PENGUIN_DATA_2_LSW,Value);//直接寄存器操作
        }

        Xil_Out32(PENGUIN_DATA_0_LSW,~((u32)1         usleep(500000);//延时

    }
}

---------------------
作者:wugz89
来源:CSDN
原文:https://blog.csdn.net/wugz89/article/details/78996553

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