Zynq Zed Device Tree

device tree最开始的是skeleton.dtsi
/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/

/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};

这是32位体系架构的设备树的skeleton,address-cells那行表示的是用32bit表示地址,寄存器也是用32bit来表示。接下来设备树里的东西是和zynq-7000这款芯片cpu息息相关的定义。将cpu以及外设都定义在此处。
《zynq-7000.dtsi》
1 /*
2 * Copyright (C) 2011 - 2014 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13 /include/ "skeleton.dtsi"
14
15 / {
16 compatible = "xlnx,zynq-7000";
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
27 clock-latency = <1000>;
28 cpu0-supply = <&regulator_vccpint>;
29 operating-points = <
30 /* kHz uV */
31 666667 1000000
32 333334 1000000
33 >;
34 };
35
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 clocks = <&clkc 3>;
41 };
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49 };
50
51 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 amba: amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 interrupt-parent = <&intc>;
65 ranges;
66
67 adc: adc@f8007100 {
68 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
70 interrupts = <0 7 4>;
71 interrupt-parent = <&intc>;
72 clocks = <&clkc 12>;
73 };
74
75 can0: can@e0008000 {
76 compatible = "xlnx,zynq-can-1.0";
77 status = "disabled";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
85 };
86
87 can1: can@e0009000 {
88 compatible = "xlnx,zynq-can-1.0";
89 status = "disabled";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
97 };
98
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
101 #gpio-cells = <2>;
102 #interrupt-cells = <2>;
103 clocks = <&clkc 42>;
104 gpio-controller;
105 interrupt-controller;
106 interrupt-parent = <&intc>;
107 interrupts = <0 20 4>;
108 reg = <0xe000a000 0x1000>;
109 };
110
111 i2c0: i2c@e0004000 {
112 compatible = "cdns,i2c-r1p10";
113 status = "disabled";
114 clocks = <&clkc 38>;
115 interrupt-parent = <&intc>;
116 interrupts = <0 25 4>;
117 reg = <0xe0004000 0x1000>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 };
121
122 i2c1: i2c@e0005000 {
123 compatible = "cdns,i2c-r1p10";
124 status = "disabled";
125 clocks = <&clkc 39>;
126 interrupt-parent = <&intc>;
127 interrupts = <0 48 4>;
128 reg = <0xe0005000 0x1000>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
133 intc: interrupt-controller@f8f01000 {
134 compatible = "arm,cortex-a9-gic";
135 #interrupt-cells = <3>;
136 interrupt-controller;
137 reg = <0xF8F01000 0x1000>,
138 <0xF8F00100 0x100>;
139 };
140
141 L2: cache-controller@f8f02000 {
142 compatible = "arm,pl310-cache";
143 reg = <0xF8F02000 0x1000>;
144 interrupts = <0 2 4>;
145 arm,data-latency = <3 2 2>;
146 arm,tag-latency = <2 2 2>;
147 cache-unified;
148 cache-level = <2>;
149 };
150
151 mc: memory-controller@f8006000 {
152 compatible = "xlnx,zynq-ddrc-a05";
153 reg = <0xf8006000 0x1000>;
154 };
155
156 ocmc: ocmc@f800c000 {
157 compatible = "xlnx,zynq-ocmc-1.0";
158 interrupt-parent = <&intc>;
159 interrupts = <0 3 4>;
160 reg = <0xf800c000 0x1000>;
161 };
162
163 uart0: serial@e0000000 {
164 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
165 status = "disabled";
166 clocks = <&clkc 23>, <&clkc 40>;
167 clock-names = "uart_clk", "pclk";
168 reg = <0xE0000000 0x1000>;
169 interrupts = <0 27 4>;
170 };
171
172 uart1: serial@e0001000 {
173 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
174 status = "disabled";
175 clocks = <&clkc 24>, <&clkc 41>;
176 clock-names = "uart_clk", "pclk";
177 reg = <0xE0001000 0x1000>;
178 interrupts = <0 50 4>;
179 };
180
181 spi0: spi@e0006000 {
182 compatible = "xlnx,zynq-spi-r1p6";
183 reg = <0xe0006000 0x1000>;
184 status = "disabled";
185 interrupt-parent = <&intc>;
186 interrupts = <0 26 4>;
187 clocks = <&clkc 25>, <&clkc 34>;
188 clock-names = "ref_clk", "pclk";
189 #address-cells = <1>;
190 #size-cells = <0>;
191 };
192
193 spi1: spi@e0007000 {
194 compatible = "xlnx,zynq-spi-r1p6";
195 reg = <0xe0007000 0x1000>;
196 status = "disabled";
197 interrupt-parent = <&intc>;
198 interrupts = <0 49 4>;
199 clocks = <&clkc 26>, <&clkc 35>;
200 clock-names = "ref_clk", "pclk";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 };
204
205 qspi: spi@e000d000 {
206 clock-names = "ref_clk", "pclk";
207 clocks = <&clkc 10>, <&clkc 43>;
208 compatible = "xlnx,zynq-qspi-1.0";
209 status = "disabled";
210 interrupt-parent = <&intc>;
211 interrupts = <0 19 4>;
212 reg = <0xe000d000 0x1000>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 };
216
217 smcc: memory-controller@e000e000 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 status = "disabled";
221 clock-names = "memclk", "aclk";
222 clocks = <&clkc 11>, <&clkc 44>;
223 compatible = "arm,pl353-smc-r2p1";
224 interrupt-parent = <&intc>;
225 interrupts = <0 18 4>;
226 ranges ;
227 reg = <0xe000e000 0x1000>;
228 nand0: flash@e1000000 {
229 status = "disabled";
230 compatible = "arm,pl353-nand-r2p1";
231 reg = <0xe1000000 0x1000000>;
232 #address-cells = <0x1>;
233 #size-cells = <0x1>;
234 };
235 nor0: flash@e2000000 {
236 status = "disabled";
237 compatible = "cfi-flash";
238 reg = <0xe2000000 0x2000000>;
239 #address-cells = <1>;
240 #size-cells = <1>;
241 };
242 };
243
244 gem0: ethernet@e000b000 {
245 compatible = "cdns,zynq-gem", "cdns,gem";
246 reg = <0xe000b000 0x1000>;
247 status = "disabled";
248 interrupts = <0 22 4>;
249 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
250 clock-names = "pclk", "hclk", "tx_clk";
251 #address-cells = <1>;
252 #size-cells = <0>;
253 };
254
255 gem1: ethernet@e000c000 {
256 compatible = "cdns,zynq-gem", "cdns,gem";
257 reg = <0xe000c000 0x1000>;
258 status = "disabled";
259 interrupts = <0 45 4>;
260 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
261 clock-names = "pclk", "hclk", "tx_clk";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 };
265
266 sdhci0: sdhci@e0100000 {
267 compatible = "arasan,sdhci-8.9a";
268 status = "disabled";
269 clock-names = "clk_xin", "clk_ahb";
270 clocks = <&clkc 21>, <&clkc 32>;
271 interrupt-parent = <&intc>;
272 interrupts = <0 24 4>;
273 reg = <0xe0100000 0x1000>;
274 };
275
276 sdhci1: sdhci@e0101000 {
277 compatible = "arasan,sdhci-8.9a";
278 status = "disabled";
279 clock-names = "clk_xin", "clk_ahb";
280 clocks = <&clkc 22>, <&clkc 33>;
281 interrupt-parent = <&intc>;
282 interrupts = <0 47 4>;
283 reg = <0xe0101000 0x1000>;
284 };
285
286 slcr: slcr@f8000000 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
290 reg = <0xF8000000 0x1000>;
291 ranges;
292 clkc: clkc@100 {
293 #clock-cells = <1>;
294 compatible = "xlnx,ps7-clkc";
295 fclk-enable = <0xf>;
296 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
297 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
298 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
299 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
300 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
301 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
302 "gem1_aper", "sdio0_aper", "sdio1_aper",
303 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
304 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
305 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
306 "dbg_trc", "dbg_apb";
307 reg = <0x100 0x100>;
308 };
309
310 rstc: rstc@200 {
311 compatible = "xlnx,zynq-reset";
312 reg = <0x200 0x48>;
313 #reset-cells = <1>;
314 syscon = <&slcr>;
315 };
316
317 pinctrl0: pinctrl@700 {
318 compatible = "xlnx,pinctrl-zynq";
319 reg = <0x700 0x200>;
320 syscon = <&slcr>;
321 };
322 };
323
324 dmac_s: dmac@f8003000 {
325 compatible = "arm,pl330", "arm,primecell";
326 reg = <0xf8003000 0x1000>;
327 interrupt-parent = <&intc>;
328 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
329 "dma4", "dma5", "dma6", "dma7";
330 interrupts = <0 13 4>,
331 <0 14 4>, <0 15 4>,
332 <0 16 4>, <0 17 4>,
333 <0 40 4>, <0 41 4>,
334 <0 42 4>, <0 43 4>;
335 #dma-cells = <1>;
336 #dma-channels = <8>;
337 #dma-requests = <4>;
338 clocks = <&clkc 27>;
339 clock-names = "apb_pclk";
340 };
341
342 devcfg: devcfg@f8007000 {
343 compatible = "xlnx,zynq-devcfg-1.0";
344 interrupt-parent = <&intc>;
345 interrupts = <0 8 4>;
346 reg = <0xf8007000 0x100>;
347 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
348 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
349 syscon = <&slcr>;
350 };
351
352 global_timer: timer@f8f00200 {
353 compatible = "arm,cortex-a9-global-timer";
354 reg = <0xf8f00200 0x20>;
355 interrupts = <1 11 0x301>;
356 interrupt-parent = <&intc>;
357 clocks = <&clkc 4>;
358 };
359
360 ttc0: timer@f8001000 {
361 interrupt-parent = <&intc>;
362 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
363 compatible = "cdns,ttc";
364 clocks = <&clkc 6>;
365 reg = <0xF8001000 0x1000>;
366 };
367
368 ttc1: timer@f8002000 {
369 interrupt-parent = <&intc>;
370 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
371 compatible = "cdns,ttc";
372 clocks = <&clkc 6>;
373 reg = <0xF8002000 0x1000>;
374 };
375
376 scutimer: timer@f8f00600 {
377 interrupt-parent = <&intc>;
378 interrupts = <1 13 0x301>;
379 compatible = "arm,cortex-a9-twd-timer";
380 reg = <0xf8f00600 0x20>;
381 clocks = <&clkc 4>;
382 };
383
384 usb0: usb@e0002000 {
385 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
386 status = "disabled";
387 clocks = <&clkc 28>;
388 interrupt-parent = <&intc>;
389 interrupts = <0 21 4>;
390 reg = <0xe0002000 0x1000>;
391 phy_type = "ulpi";
392 };
393
394 usb1: usb@e0003000 {
395 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
396 status = "disabled";
397 clocks = <&clkc 29>;
398 interrupt-parent = <&intc>;
399 interrupts = <0 44 4>;
400 reg = <0xe0003000 0x1000>;
401 phy_type = "ulpi";
402 };
403
404 watchdog0: watchdog@f8005000 {
405 clocks = <&clkc 45>;
406 compatible = "cdns,wdt-r1p2";
407 interrupt-parent = <&intc>;
408 interrupts = <0 9 1>;
409 reg = <0xf8005000 0x1000>;
410 timeout-sec = <10>;
411 };
412 };
413 };

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