CORE IP生成的加法器在MAP时报错

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nongfuxu 的头像
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Joined: 01/11/2012
积分: 70

用SCH格式重新建了项目,在项目中加入了CORE IP生成的24int和28uint相加的加法器,然后在MAP时出现以下错误信息:
MapLib:979 - LUT3 symbol "D13/D6/U0/xst_addsub/i_baseblox.i_baseblox_addsub/pipelining.stages[1].slices[1].first.first_stage_adder/i_lut4.i_lut4_addsub/halfsum<0>1" (output signal=D13/D6/U0/xst_addsub/i_baseblox.i_baseblox_addsub/pipelining.stages[1].slices[1].first.first_stage_adder/i_lut4.i_lut4_addsub/halfsum<0>) has input signal "D13/D6/bypass" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.
哪位大侠知道是什么原因?

shaweikang1984 的头像
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Joined: 04/15/2011
积分: 16

检查下设计是不是有输入信号是悬空的

或者你在map选项中添加“-u”

paradoxfx 的头像
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Joined: 02/11/2010
积分: 1099

信息太少,找不到原因啊,再看看 Section 5 of the Map Report 讲的什么?