module mux41(
input [1:0] S,
input [3:0] C,
output Z
);
reg Z;

always@(S or C)
begin
case(S)
2'b00: Z<=C[0];
2'b01: Z<=C[1];
2'b10: Z<=C[2];
2'b11: Z<=C[3];
endcase
end

endmodule
提示line 26 Illegal redeclaration of 'Z'，那位大侠知道是怎么回事啊