最近在学xilinx 的FPGA，一个很简单的计数功能的Verilog语言编写的
在仿真时，报错：
ERROR:Simulator:606 - ISE Simulator is unable to compile this design due to
specific coding constructs used in design unit work/counter, defined in file
"F:/Program File/Xilinx/counter/counter.v". Xilinx is actively working on
reducing the number of conditions where this error occurs. For more
information on this error, please consult Answer Record 24068 in Answers
Database at http://www.xilinx.com/support.

我也去http://www.xilinx.com/support网站，看了下24068，是不是从新下载就行？那下载下面的哪个？
ISE Foundation - 9.1i Full Product Installation
Embedded Development Kit - 9.1i Full Product Installation
AccelDSP Synthesis Tool - 9.1i Full Product Installation
System Generator - 9.1i Full Product Installation
我注册了帐号，可是总是通不过，不知道怎么搞的，哪位大侠帮我下？？？