版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/qq_37512669/article/details/90418973
软件：Vivado2017.4 板卡：Ego1 型号：xc7a35tcsg324-1
六、纯Verilog实现数字钟
clock1_top.v
`timescale 1ns / 1ps
module clock1_top(
input clk_100MHz,
input clr,
input en,
input mode,
input inc,
output [7:0]a_to_h_0,
output [7:0]a_to_h_1,
output [7:0]an
);
wire clk_200Hz;
wire clk_10Hz;
wire clk_1Hz;
wire [7:0]hour;
wire [7:0]min;
wire [7:0]sec;
wire incd;
wire moded;
wire [7:0]a_to_g_hour;
wire [7:0]a_to_g_min;
wire [7:0]a_to_g_sec;
wire [2:0]blink;
wire [3:0]dp;
clk_div U1(.clk_100MHz(clk_100MHz),
.clk_200Hz(clk_200Hz),
.clk_10Hz(clk_10Hz),
.clk_1Hz(clk_1Hz)
);
debounce2 U2(.clk_200Hz(clk_200Hz),
.clr(~clr),
.inp({inc,mode}),
.outp({incd,moded})
);
clocks_ctrl U3(.clk_1Hz(clk_1Hz),
.clk_10Hz(clk_10Hz),
.clr(~clr),
.en(en),
.mode(moded),
.inc(incd),
.hour(hour),
.min(min),
.sec(sec),
.blink(blink)
);
bindcb8 U4(.b(hour),
.p(a_to_g_hour)
);
bindcb8 U5(.b(min),
.p(a_to_g_min)
);
bindcb8 U6(.b(sec),
.p(a_to_g_sec)
);
x8seg_clock U7(.clk(clk_200Hz),
.x({a_to_g_min,a_to_g_sec}),
.blink(blink[1:0]),
.dp(4'b0100),
.a_to_h(a_to_h_0),
.an(an[3:0])
);
x8seg_clock U8(.clk(clk_200Hz),
.x({8'b0,a_to_g_hour}),
.blink({1'b0,blink[2]}),
.dp(4'b0001),
.a_to_h(a_to_h_1),
.an(an[7:4])
);
endmodule
clk_div.v
`timescale 1ns / 1ps
module clk_div(
input clk_100MHz,
output clk_200Hz,
output clk_10Hz,
output clk_1Hz
);
reg[17:0]cnt_200Hz;
reg[8:0]cnt_10Hz;
reg[9:0]cnt_1Hz;
reg clk_1KHz_reg;
reg clk_200Hz_reg;
reg clk_10Hz_reg;
reg clk_1Hz_reg;
initial
begin
cnt_10Hz =0;
cnt_1Hz =0;
clk_200Hz_reg =0;
clk_10Hz_reg =0;
clk_1Hz_reg= 0;
end
always@(posedge clk_100MHz)
begin
if(cnt_200Hz ==18'h3D08F)
begin
clk_200Hz_reg<=~clk_200Hz_reg;
cnt_200Hz<=0;
end
else
cnt_200Hz<=cnt_200Hz+1;
end
always@(posedge clk_200Hz)
begin
if(cnt_10Hz ==4'h9)
begin
clk_10Hz_reg<=~clk_10Hz_reg;
cnt_10Hz<=0;
end
else
cnt_10Hz<=cnt_10Hz+1;
end
always@(posedge clk_200Hz)
begin
if(cnt_1Hz ==7'h63)//99
begin
clk_1Hz_reg<=~clk_1Hz_reg;
cnt_1Hz<=0;
end
else
cnt_1Hz<=cnt_1Hz+1;
end
assign clk_200Hz = clk_200Hz_reg;
assign clk_10Hz = clk_10Hz_reg;
assign clk_1Hz = clk_1Hz_reg;
endmodule
debounce2.v
`timescale 1ns / 1ps
module debounce2(
input clk_200Hz,
input clr,
input[1:0]inp,
input[1:0]outp
);
reg[1:0]delay1;
reg[1:0]delay2;
reg[1:0]delay3;
always@(posedge clk_200Hz or posedge clr)
begin
if(clr == 1)
begin
delay1 <=2'b00;
delay2 <=2'b00;
delay3 <=2'b00;
end
else
begin
delay1 <=inp;
delay1 <=delay1;
delay1 <=delay2;
end
end
assign outp=delay1&delay2&delay3;
endmodule
clocks_ctrl.v
`timescale 1ns / 1ps
module clocks_ctrl(
input clk_1Hz,
input clk_10Hz,
input clr,
input en,
input mode,
input inc,
output reg[7:0]hour,
output reg[7:0]min,
output reg[7:0]sec,
output reg[2:0]blink
);
reg [3:0]cnt;
reg inc_reg;
reg[1:0]state;
parameter state0 = 2'b00,state1 = 2'b01,state2 = 2'b10,state3 = 2'b11;
initial
begin
state = 2'b0;
cnt = 4'b0000;
end
always@(posedge mode)
begin
state<= state+1;
end
always@(posedge clk_10Hz)
begin
if(clr)
begin
hour<=8'b0;
min<=8'b0;
sec<=8'b0;
end
else if(en)
begin
hour<=hour;
min<=min;
sec<=sec;
end
else
begin
case(state)
state0:
begin
if(cnt == 4'd9)
begin
cnt=0;
if(sec ==8'd59)
begin
sec<=0;
if(min==8'd59)
begin
min<=0;
if(hour==8'd23)
hour <=0;
else
hour <=hour+1;
end
else
min<=min+1;
end
else
sec<=sec+1;
end
else
cnt =cnt+1;
end
state1:
begin
if(inc)
begin
if(!inc_reg)
begin
inc_reg<=1;
if(hour==8'd23)
hour<=0;
else
hour<=hour+1;
end
end
else
inc_reg <=0;
end
state2:
begin
if(inc)
begin
if(!inc_reg)
begin
inc_reg<=1;
if(min==8'd59)
min<=0;
else
min<=min+1;
end
end
else
inc_reg<=0;
end
state3:
begin
if(inc)
begin
if(!inc_reg)
begin
inc_reg<=1;
if(sec==8'd59)
sec<=0;
else
sec<=sec+1;
end
end
else
inc_reg<=0;
end
endcase
end
end
always@(state or clk_1Hz)
begin
case(state)
state0:blink[2:0]<=3'b111;
state1:
begin
blink[2:0]<=3'b111;
blink[2]<=clk_1Hz;
end
state2:
begin
blink[2:0]<=3'b111;//blink[2]<=0;//
blink[1]<=clk_1Hz;
end
state3:
begin
blink[2:0]<=3'b111;
blink[0]<=clk_1Hz;
end
default:blink[2:0]<=3'b111;
endcase
end
endmodulebindcb8.v
`timescale 1ns / 1ps
module bindcb8(
input wire[7:0]b,
output reg[9:0]p
);
reg [17:0]z;
integer i;
always@(*)
begin
for(i=0;i<=17;i=i+1)
z[i] =0;
z[10:3] =b;
repeat(5)
begin
if(z[11:8]>4)
z[11:8] = z[11:8]+3;
if(z[15:12]>4)
z[15:12]=z[15:12]+3;
z[17:1] = z[16:0];
end
p=z[17:8];
end
endmodule
x8seg_clock.v
`timescale 1ns / 1ps
module x8seg_clock(
input wire clk,
input[15:0]x,
input[1:0]blink,
input[3:0]dp,
output reg[7:0]a_to_h,
output reg[3:0]an
);
reg[3:0]digit;
reg[1:0]s;
initial
begin
s=0;
end
always@(*)
case(s)
0:digit =x[3:0];
1:digit =x[7:4];
2:digit =x[11:8];
3:digit =x[15:12];
endcase
always@(*)
case(digit)
0:a_to_h = {8'b1111110,dp[s]};
1:a_to_h = {8'b0110000,dp[s]};
2:a_to_h = {8'b1101101,dp[s]};
3:a_to_h = {8'b1111001,dp[s]};
4:a_to_h = {8'b0110011,dp[s]};
5:a_to_h = {8'b1011011,dp[s]};
6:a_to_h = {8'b1011111,dp[s]};
7:a_to_h = {8'b1110000,dp[s]};
8:a_to_h = {8'b1111111,dp[s]};
9:a_to_h = {8'b1111011,dp[s]};
'hA:a_to_h = {8'b1110111,dp[s]};
'hB:a_to_h = {8'b0011111,dp[s]};
'hC:a_to_h = {8'b1001110,dp[s]};
'hD:a_to_h = {8'b0111101,dp[s]};
'hE:a_to_h = {8'b1001111,dp[s]};
'hF:a_to_h = {8'b1000111,dp[s]};
default:a_to_h = {8'b0000000,dp[s]};//
endcase
always@(posedge clk)
begin
if(s==3)
s<=0;
else
s<=s+1;
end
always@(*)
begin
case(s)
0:an=4'b0001&{4{blink[0]}};
1:an=4'b0010&{4{blink[0]}};
2:an=4'b0100&{4{blink[1]}};
3:an=4'b1000&{4{blink[1]}};
endcase
end
endmodule
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_0[0]}]
set_property PACKAGE_PIN D4 [get_ports {a_to_h_0[7]}]
set_property PACKAGE_PIN E3 [get_ports {a_to_h_0[6]}]
set_property PACKAGE_PIN D3 [get_ports {a_to_h_0[5]}]
set_property PACKAGE_PIN F4 [get_ports {a_to_h_0[4]}]
set_property PACKAGE_PIN F3 [get_ports {a_to_h_0[3]}]
set_property PACKAGE_PIN E2 [get_ports {a_to_h_0[2]}]
set_property PACKAGE_PIN D2 [get_ports {a_to_h_0[1]}]
set_property PACKAGE_PIN H2 [get_ports {a_to_h_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_h_1[0]}]
set_property PACKAGE_PIN B4 [get_ports {a_to_h_1[7]}]
set_property PACKAGE_PIN A4 [get_ports {a_to_h_1[6]}]
set_property PACKAGE_PIN A3 [get_ports {a_to_h_1[5]}]
set_property PACKAGE_PIN B1 [get_ports {a_to_h_1[4]}]
set_property PACKAGE_PIN A1 [get_ports {a_to_h_1[3]}]
set_property PACKAGE_PIN B3 [get_ports {a_to_h_1[2]}]
set_property PACKAGE_PIN B2 [get_ports {a_to_h_1[1]}]
set_property PACKAGE_PIN D5 [get_ports {a_to_h_1[0]}]
set_property PACKAGE_PIN P17 [get_ports clk_100MHz]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100MHz]
set_property PACKAGE_PIN P15 [get_ports clr]
set_property PACKAGE_PIN P5 [get_ports en]
set_property PACKAGE_PIN P4 [get_ports inc]
set_property PACKAGE_PIN P3 [get_ports mode]
set_property IOSTANDARD LVCMOS33 [get_ports clr]
set_property IOSTANDARD LVCMOS33 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports inc]
set_property IOSTANDARD LVCMOS33 [get_ports mode]
set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN G2 [get_ports {an[7]}]
set_property PACKAGE_PIN C2 [get_ports {an[6]}]
set_property PACKAGE_PIN C1 [get_ports {an[5]}]
set_property PACKAGE_PIN H1 [get_ports {an[4]}]
set_property PACKAGE_PIN G1 [get_ports {an[3]}]
set_property PACKAGE_PIN F1 [get_ports {an[2]}]
set_property PACKAGE_PIN E1 [get_ports {an[1]}]
set_property PACKAGE_PIN G6 [get_ports {an[0]}]
版权声明：本文为CSDN博主「李老狗在看FPGA」的原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/qq_37512669/article/details/90418973
